As transistors become more highly integrated, logic devices trend toward high speed and high integration. With high integration of the transistors, interconnections are increasingly minimized in dimension. Such minimization results in interconnection delay and impediment to high speed operation of the devices.
As an interconnection material of a large-scale integrated circuit (LSI), aluminum alloy has been used for many years. At the present time, copper (Cu) has become the most promising substitute for aluminum alloy in that copper enjoys a very low resistivity and has superior electromigration (EM) resistance properties. However, since it is difficult to etch Cu and since Cu is readily oxidized during an oxidation process, a damascene process is used to form Cu interconnections.
The damascene process includes the steps of (1) forming a groove in which an upper interconnection is formed, (2) forming a via hole connecting the upper interconnection to a lower interconnection or a substrate, (3) forming a copper layer over the resultant structure, and (4) planarizing the copper layer by means of a chemical mechanical polishing (CMP). In this manner, the damascene process is a form of filling process.
A low-k dielectric makes it possible to lower the resulting parasitic capacitance between interconnections, enhance device operating speed, and suppress the crosstalk phenomenon. In view of these advantages, the low-k dielectric has been developed in various ways. Generally, the low-k dielectric is classified into a silicon dioxide (SiO2) group organic polymer and a carbon (C) group organic polymer.
In a typical damascene process employing an insulating layer made of organic polymer, a dual hard mask is used because the organic polymer may be damaged by oxygen plasma when a photoresist layer is ashed. In addition, when a rework process is employed wherein a photoresist pattern is removed so as to re-perform the photolithographic process because the initial photolithographic process was incorrect, an insulating layer formed of the organic polymer can become significantly damaged. Accordingly, in the case where an insulating layer formed of organic polymer is used, a dual hard mask is used instead of a single hard mask. That is, a second hard mask operating as a capping layer is formed on the organic polymer insulating layer. The capping layer serves to prevent damage to the organic polymer insulating layer.
A conventional dual damascene process employing a dual hard mask is now described with reference to FIG. 1A through FIG. 1I.
Referring to FIG. 1A, a lower etch-stop layer 105, a lower insulating layer 110, an upper etch-stop layer 115, an upper insulating layer 120, a bottom hard mask layer 125, and a top hard mask layer 130 are sequentially formed on a semiconductor substrate 100.
Referring to FIG. 1B, a photoresist pattern 135 having the opening of a groove pattern is formed on the top hard mask layer 130. Reference symbol “D1” denotes the width of the groove pattern. Using the photoresist pattern 135 as a mask, the top hard mask layer 130 is patterned to form a groove opening 133 exposing a surface of the bottom hard mask layer 125.
Referring to FIG. 1C, the photoresist pattern 135 is removed by ashing. The groove pattern 133 is formed in the top hard mask layer 130.
Referring to FIG. 1D, a photoresist pattern 140 having an opening of the width of an underlying via hole to be formed is provided on the exposed bottom hard mask layer 125. Reference symbol “D2” denotes the width of the hole pattern. Following the photolithographic process for forming the photoresist pattern 140, a photoresist tail 141 may be created due to the lack of a depth of focus (DOF) margin. The lack of the DOF margin is caused by the step difference in the hard mask layer 130. In a subsequent process, the photoresist tail 141 can result in an incorrect pattern, which can prevent the formation of a stable damascene structure. In a worst case scenario, the hole pattern may not be formed.
Referring to FIG. 1E, using the photoresist pattern 140 as a mask, the bottom hard mask layer 125 is patterned to expose a surface of the upper insulating layer 120.
Referring to FIG. 1F, using the bottom hard mask layer 125 as a mask, the upper insulating layer 120 is etched to expose a surface of the upper etch-stop layer 115. A hole opening 143 is formed in the upper insulating layer 120. The hole opening 143 is narrower than the groove opening 133. Since the upper insulating layer 120 is formed of the same carbon-group material as the photoresist pattern 140, their etching rates are similar to each other. Thus, when the upper insulating layer 120 is etched, the photoresist pattern 140 is removed at the same time.
Referring to FIG. 1G, using the patterned top hard mask layer 130 as a mask, the bottom hard mask layer 125 and the exposed upper etch-stop layer 115 are etched to expose a top surface of the upper insulating layer 120 adjacent to the hole opening 143 and the lower insulating layer 110 under the hole opening 143. When the bottom hard mask layer 125 is patterned using the top hard mask layer 130 as a mask, a facet 147 may be formed. The facet 147 has a sloped profile, which is made by etching the edge of the pattern. In the case where low etch selectivity exists between top and bottom hard mask layers or where the top hard mask layer is relatively thin, the resulting facet 147 is relatively larger. The facet 147 causes a difficulty in isolation between adjacent interconnections in subsequent processes. In order to overcome this difficulty, it is preferable to use materials having a high etch selectivity between the top and bottom hard mask layers or to thickly form the upper hard mask layer. Unfortunately, such materials are rare, and the thick upper hard mask layer worsens the step difference of the pattered hard mask layer (see FIG. 1D). Due to the larger step difference, the resulting photoresist tail becomes a more serious concern. In addition, this larger step difference results in difficulty in removing the upper hard mask layer during subsequent processes.
Referring to FIG. 1H, the exposed upper insulating layer 120 and the exposed lower insulating layer 110 are patterned to form a groove 145 in the upper insulating layer and to form a hole 150 in the lower insulating layer at the same time. The resulting hole 150 is narrower than the groove 145.
Referring to FIG. 1I, the lower etch-stop layer 105 below the via hole 150 is removed to expose a surface of the semiconductor substrate 100. As a result, a damascene pattern is formed. At this time, the upper hard mask layer 130 and the exposed upper etch-stop layer 115 below the groove 145 may also be removed. Although not shown in this figure, the groove 145 and the via hole 150 are filled with a conductive material and planarized to form an interconnection and a via plug. In the case where the distance between grooves is relatively short, a profile having a sharp protrusion 148 is made by the facet, as shown in FIG. 2. During a chemical mechanical polishing (CMP) process performed after a damascene pattern is formed and a conductive layer is deposited, the protrusion 148 impedes the isolation between interconnections and allows for a conductive bridge to be formed therebetween. The CMP process can therefore be performed below target, which results in poor polishing uniformity.